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Hi Everyone,

During this meeting, we will have two topics: MPAM and Flush by PA range - need for a mini subsystem

1. For the MPAM, Zeng Heng has developed some other new features such as Enable PARTID-narrow Feature, MPAM Extension Feature InterfaceMPAM, needs to discuss further, and also some Bugfix waiting for approve. Details as attached.

2. The second topic is from Jonathan:

Flush by PA range - need for a mini subsystem :

This is needed for CXL and we've jumped through various possible ways to handle it.

1. PSCI call (not currently in spec)
     Doesn't work well as 'only' solution as some hardware provides direct memory mapped IO interfaces for this.

2. ACPI wrapping of both PSCI call and memory mapped.
     Unfortunately you can wrap SCMI (via a PCC channel) but not (as I understand  it SMCCC) so I don't think an ACPI wrapper in general works.

3. Current option:  Face up to the fact we need to just do this kernel first with drivers for the various hardware that surfaces.  We aren't particularly far into a design yet so maybe email is fine for now if people are busy.

For this I'm thinking a really small subsystem / class.
Lots of design options but one might be

1. Driver registers with class and provides PA ranges for which it needs to be notified (simpler option is it gets notified of everything)Class is there for user space to be able to see what is involved...

2. Notification chain follows similar design to MMU notifiers, just on physical addresses and global rather than tied to each mm.

Requirements for design:

1. Multiple entities may need to be told to flush for a given range (interleaving etc may be going on).

2. Flush should be range. Any hardware that doesn't support range will need to flush everything.

3. Support rich set of flushes. Drivers may have to upgrade the lighter ones to what they support (cache coherency protocols all allow this so should be technically fine to do rather than reject the flush)Other things I've forgotten?

In particular I'd like any insights people have on plausible hardware designs that this approach might not work for.A sticky corner is how to know that all drivers for architecturally necessary flushes are present.  Easy to check if there is one covering the range, no so easy to check if one instance of an interleaves solution is missing.
We can probably solve this at the individual driver level, but it's ugly.

Anyone with a discussion topic feel free to ping the list  linaro-open-discussions@op-lists.linaro.org to find an existing call or arrange a specific one.

 One important aspect of the main open discussion list is to facilitate dialog with maintainers in the Arm ecosystem.

Linaro Open Discussions monthly meeting

When：Oct, 22, 12:00 – 13:00pm BST

Wherehttps://linaro-org.zoom.us/j/95682500341 (map)

11:00 Linaro Open Discussions monthly meeting（for this meeting）

where：Join Zoom Meeting
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